IMEC Claims Coarse-Grain Processor Breakthrough
Posted by Sachin Garg on 26th October 2005 | Permanent Link
Some more excerpts from the original article:
Benchmark studies for a 32bit ADRES core with 8×8 functional units in a 90nm CMOS technology, showed power efficiency in the range of 50 to 60MOPS per milli-watts; peak performance around 25GOPS (400MHz); an area of 7 millimeters squared including the core and the L1 cache, which is 32KB data, 128KB instruction and 16KB configuration memory.
The performance of compiled C-code on the ADRES core is 10 times better in terms of cycles than compiled code on state-of-the-art DSP solutions. Even when using C-code compilation, ADRES achieves an improved performance compared to current state-of-the-art assembly-programmed approaches, IMEC reported.
Breakthrough specifications were achieved by the unique architecture of the core, parallelism and compiler optimization, IMEC explained. ADRES combines the host VLIW processor and configurable accelerator in a single architecture, leading to simplified programming and removal of communication bottleneck.